The present invention relates to data processing systems and, in particular, to a system bus for use in such systems which utilize CMOS circuitry. The present invention concerns a control for such a bus whereby inactivity on the bus is sensed and the bus is subsequently driven to a defined logic level.
In computer systems and other data processing systems, a bus is commonly employed to interconnect the various elements of the systems. For example, a central processing unit is typically connected to elements such as memory devices, input/output devices, etc. via a bus capable of carrying the signals associated with the operation of each element. These signals include, for example, data signals, clock signals and other control signals. The bus must be capable of carrying such signals to all of the elements coupled to it so that the desired operation can be carried out by the computer system.
Because the bus is utilized in virtually every operation performed by the computer system, it is a key element whose characteristics have a major impact on overall performance of the system. For example, the speed of an operation is limited to a degree by the bus since many of the signals within the computer must be transmitted via the bus to the appropriate element; thus, the speed at which the bus is capable of responding to and carrying data is a critical consideration.
One attempt to achieve higher speed on a bus involves the use of a circuit to restore the bus to a known level, such as one of the logical levels of the bus. However, restoring the bus to one of the logic levels tends to increase the speed of switching in only one direction, i.e., either the rising or falling edge.
Furthermore, the reason for restoring the bus to one of the logic levels is to prevent the bus from assuming a level intermediate to a high and low level during periods of inactivity on the bus. In conventional systems, such an intermediate level needs to be avoided since it causes input receivers to be biased as linear amplifiers instead of as digital logic gates. When operating as linear amplifiers the input receivers dissipate excessive power which might result in permanent damage to the bus receiver circuits
In order to increase the speed of the rising and falling edges and avoid this excess power, a central resource can be used to detect periods of inactivity on the bus and then, during such periods, force the bus to one of the logical levels thus eliminating the intermediate bias level on the input receivers connected to the bus. The operation of forcing the bus to one of the logical levels during periods of inactivity is referred to as "defaulting" the bus. On a bus where there is no single resource with enough information to determine when the bus should be defaulted, this simple approach cannot be used.